The preset invention generally relates to a CAD method and CAD apparatus for aiding layout design of semiconductor integrated circuits such as VLSI, and more particularly to data-path automatic layout method and apparatus for automatically executing a layout design of a data-path logic circuit which performs arithmetic processing of data signals of plural bits.
Recently, manufacturing technologies for semiconductor integrated circuits have been greatly improved. Especially, nowadays development of fine machining technologies and multi-layer wiring technologies makes it feasible to mount more than 10 millions of transistors on a single chip. However, it was difficult for conventional design aid systems or design automation technologies using computers to accomplish circuit design of such a large-scale semiconductor integrated circuit, because time required for the computer to process design data increases with increasing number of logic elements to be designed, accompanied with deterioration of quality in the processing result.
A signal processing circuit is generally required to have high performance and small area. In designing a layout of such a signal processing circuit, a method of determining the layout based on an automatic layout technology is not used. The method having been normally adopted is rather to dispose each constituent element on a substrate so as to form the same layout as that of a logic circuit diagram, for example for the purpose of making great account of signal flow.
On the other hand, a data-path automatic layout method not relying on the arrangement of a logic circuit diagram is for example disclosed in the unexamined Japanese patent application No. 3-77172/1991, which comprises steps of designating bit information through manual operation, clustering bit slice elements based on this designation, and automatically obtaining a layout.
However, according to the conventional layout design method directly copying the layout of the logic circuit diagram, there is a possibility that a resultant layout is worsened in area efficiency because any areal correlation is not recognized between the constituent element of the logic circuit diagram (i.e. logic symbol) and the actual component handled in the layout.
A method of improving this drawback is for example a bit slice method which comprises steps of preparing a logic element unifying a series of arithmetic processes corresponding to a one-bit signal on a logic circuit diagram, preparing a physical element (cell) realizing these arithmetic processes, disposing logic elements as much as the number of bits of signals, and accomplishing the layout by superposing cells as much as the number of bits of signals so as to obtain a layout similar to that of the logic circuits. However, it is mandatorily required to prepare numerous kinds of cells so as to meet various circuits, which will cause a problem of increasing the manufacturing time.
More specifically, FIGS. 19A and 19B show exemplary layout results obtained according to the conventional data-path automatic layout method, while FIG. 20 shows an overall layout of a semiconductor integrated circuit realized by the conventional data-path automatic layout method. In these drawings, reference numeral 20 represents a data-path block, reference numeral 22 represents a dedicated cell, reference numeral 24 represents an input terminal, reference numeral 28 represents an output terminal, reference numeral 30 represents a semiconductor integrated circuit, reference numeral 32 represents a data-path wiring, and reference numeral 34 represents a peripheral circuit.
In such a conventional data-path automatic layout method, optimization of performance and area is feasible only when the bit number of signals is constant throughout the processing in the circuit as shown in FIG. 19A. If the bit number of signals is varied through the processing in the circuit as shown in FIG. 19B, it is not possible to obtain an effective layout. To solve this problem, it is necessary to newly develop dedicated elements in accordance with the given bit arrangement, which will inevitably require manual correction and possibly increase the entire cost for developing semiconductor integrated circuits.
Furthermore, as shown in FIGS. 19A and 19B, the positional relationship between input terminal 24 and output terminal 26 in the data-path block 20 is univocally or forcibly determined according to the given bit arrangement. For this reason, each data-path wiring 32 may be subjected to undesirable bending as shown in FIG. 20. Such a bending will worsen the performance and area efficiency when the semiconductor integrated circuit 30 is evaluated as a whole.
One method for disposing the terminals at desirable positions is an automatic layout method according to the standard cell method. However, the existing automatic layout methods are normally used for optimizing the wiring, and not applicable to the optimization of performance and area of data-path logic circuits.